44 research outputs found

    Reservoir Computing Approach to Robust Computation using Unreliable Nanoscale Networks

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    As we approach the physical limits of CMOS technology, advances in materials science and nanotechnology are making available a variety of unconventional computing substrates that can potentially replace top-down-designed silicon-based computing devices. Inherent stochasticity in the fabrication process and nanometer scale of these substrates inevitably lead to design variations, defects, faults, and noise in the resulting devices. A key challenge is how to harness such devices to perform robust computation. We propose reservoir computing as a solution. In reservoir computing, computation takes place by translating the dynamics of an excited medium, called a reservoir, into a desired output. This approach eliminates the need for external control and redundancy, and the programming is done using a closed-form regression problem on the output, which also allows concurrent programming using a single device. Using a theoretical model, we show that both regular and irregular reservoirs are intrinsically robust to structural noise as they perform computation

    Time of flight measurements based on FPGA using a breast dedicated PET

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    In this work the implementation of a Time-to-Digital Converter (TDC) using a Nutt delay line FPGA-based and applied on a Positron Emission Tomography (PET) device is going to be presented in order to check the system’s suitability for Time of Flight (TOF) measurements. In recent years, FPGAs have shown great advantages for precise time measurements in PET. The architecture employed for these measurements is described in detail. The system developed was tested on a dedicated breast PET prototype, composed of LYSO crystals and Positive Sensitive Photomultipliers (PSPMTs). Two distinct experiments were carried out for this purpose. In the first test, system linearity was evaluated in order to calibrate the time measurements, providing a linearity error of less than 2% and an average time resolution of 1.4 ns FWHM. The second set of measurements tested system resolution, resulting in a FWHM as good as 1.35 ns. The results suggest that the coincidence window for the current PET can be reduced in order to minimize the random events and thus, achieve better image qualityAguilar, A.; García Olcina, R.; Martos, J.; Soret, J.; Torres-Pais, J.; Benlloch Baviera, JM.; González Martínez, AJ.... (2014). Time of flight measurements based on FPGA using a breast dedicated PET. Journal of Instrumentation. 9:0-8. doi:10.1088/1748-0221/9/05/C05012S08

    A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

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    Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we designed and built a composable, reconfigurable hardware fabric based on field programmable gate arrays (FPGA). Each server in the fabric contains one FPGA, and all FPGAs within a 48-server rack are interconnected over a low-latency, high-bandwidth network. We describe a medium-scale deployment of this fabric on a bed of 1632 servers, and measure its effectiveness in accelerating the ranking component of the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system. Under high load, the large-scale reconfigurable fabric improves the ranking throughput of each server by 95% at a desirable latency distribution or reduces tail latency by 29% at a fixed throughput. In other words, the reconfigurable fabric enables the same throughput using only half the number of servers

    Does School Discipline Style Make a Difference?

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    The Future of Integrated Circuits: A Survey of Nanoelectronics

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    Defects and faults in QCA-based PLAs

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    FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery

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